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Tables of Contents for Firewire System Architecture
Chapter/Section Title
Page #
Page Count
About This Book
1
12
The MindShare Architecture Series
1
1
Cautionary Note
2
1
Organization of This Book
2
5
Part One: Introduction to FireWire (IEEE 1394)
2
1
Chapter 1: Why FireWire?
2
1
Chapter 2: Overview of the FireWire Architecture
2
1
Part Two: Serial Bus Communications
3
1
Chapter 3: Communication Model
3
1
Chapter 4: Communications Services
3
1
Chapter 5: Cables & Connectors
3
1
Chapter 6: The Electrical Interface
3
1
Chapter 7: Arbitration
3
1
Chapter 8: Asynchronous Packets
3
1
Chapter 9: Isochronous Packets
3
1
Chapter 10: PHY Packet Format
4
1
Chapter 11: Link to PHY Interface
4
1
Chapter 12: Transaction Retry
4
1
Part Three: Serial Bus Configuration
4
1
Chapter 13: Configuration Process
4
1
Chapter 14: Bus Reset (Initialization)
4
1
Chapter 15: Tree Identification
4
1
Chapter 16: Self Identification
4
1
Part Four: Serial Bus Management
5
1
Chapter 17: Cycle Master
5
1
Chapter 18: Isochronous Resource Manager
5
1
Chapter 19: Bus Manager
5
1
Chapter 20: Bus Management Services
5
1
Part Five: Registers and Configuration ROM
5
1
Chapter 21: CSR Architecture
5
1
Chapter 22: PHY Registers
5
1
Chapter 23: Configuration ROM
5
1
Part Six: Power Management
6
1
Chapter 24: Introduction to Power Management
6
1
Chapter 25: Cable Power Distribution
6
1
Chapter 26: Suspend & Resume
6
1
Chapter 27: Power State Management
6
1
Appendix
6
1
Example 1394 Chip Solutions
6
1
Target Audience
7
1
Prerequisite Knowledge
7
1
Documentation Conventions
7
2
Labels for Multi-byte Blocks
7
1
Hexadecimal Notation
8
1
Binary Notation
8
1
Decimal Notation
8
1
Bit Versus Byte Notation
9
1
Identification of Bit Fields (logical groups of bits or signals)
9
1
Visit Our Web Page
10
1
We Want Your Feedback
10
3
Part One Introduction to FireWire (IEEE 1394a)
13
24
Chapter 1: Why FireWire?
13
6
Overview
13
1
Motivations Behind FireWire Development
13
3
Inexpensive Alternate to Parallel Buses
14
1
Plug and Play Support
14
1
Eliminate Host Processor/Memory Bottleneck
14
1
High Speed Bus with Scalable Performance
15
1
Support for Isochronous Applications
15
1
BackPlane and Cable Environments
15
1
Bus Bridge
15
1
1394 Applications
16
1
IEEE 1394 Refinements
16
1
Primary Features
17
2
Chapter 2: Overview of the IEEE 1394 Architecture
19
18
IEEE 1394 Overview
19
1
Specifications and Related Documents
20
3
IEEE 1394-1995 and the IEEE 1394a Supplement
20
1
IEEE 1394.B
21
1
Unit Architecture Specifications
21
2
IEEE 1394 Topology
23
1
Multiport Nodes and Repeaters
23
1
Configuration
23
1
Peer-To-Peer Transfers
24
1
Device Bay
24
1
The ISO/IEC 13213 Specification
24
10
Node Architecture
25
3
Address Space
28
2
Transfers and Transactions
30
1
Asynchronous Transfers
30
2
Isochronous Transfers
32
1
Control and Status Registers (CSRs)
33
1
Configuration ROM
33
1
Message Broadcast
34
1
Interrupt Broadcast
34
1
Automatic Configuration
34
3
Part Two Serial Bus Communications
37
228
Chapter 3: Communications Model
37
28
Overview
37
2
Transfer Types
39
3
Asynchronous
40
1
Isochronous
41
1
The Protocol Layers
42
18
Bus Management Layer
44
1
Transaction Layer
45
1
Transaction Layer Services
45
2
Link Layer
47
2
Split Transactions
49
2
Concatenated Transactions
51
1
Unified Transactions
52
1
Physical Layer
53
1
Twisted Pair Signaling
54
1
Bus Configuration
55
1
Arbitration
55
1
Data Transmission
56
1
Power Pair
56
1
Packet-Based Transactions
56
1
Asynchronous Packets
56
2
Isochronous Packet
58
1
Port Repeater
59
1
A Sample Asynchronous Transaction
60
3
The Request
61
1
The Response
61
2
An Example Isochronous Transaction
63
2
Chapter 4: Communications Services
65
20
Overview
65
1
Anatomy of Asynchronous Transactions
66
12
The Request Subaction
66
3
Initiating the Transaction (The Request)
69
1
Transaction Layer
69
1
The Link Layer
69
1
The PHY Layer
70
1
Receiving the Request (The Indication)
71
1
Physical Layer
71
1
Link Layer
71
1
Transaction Layer
72
1
The Acknowledgment
72
1
Response Subaction
73
1
Reporting the Results (The Response)
74
1
Transaction Layer Response
74
1
Link Layer Response
75
1
PHY Layer Response
75
1
Response Reception
76
1
Physical Layer
76
1
Link Layer
76
1
Transaction Layer
77
1
The Acknowledgment
77
1
Transaction Label
78
1
Anatomy of Isochronous Transactions
78
7
Setting Up Isochronous Transactions
79
1
Maintaining Synchronization
79
1
Isochronous Transactions
80
1
Isochronous Transaction Initiation & Reception
80
1
Initiating the Transaction
81
1
Link Layer
81
1
The PHY Layer
81
1
Transaction Reception
82
1
Physical Layer
83
1
Link Layer
83
2
Chapter 5: Cables & Connectors
85
10
Cable and Connector Types
85
4
6-pin Connector (1394-1995)
86
1
Make First/Break Last Power Pins
87
1
Optional 4-pin Connector (1394a supplement)
87
1
Positive Retention
88
1
Cable Characteristics
89
3
6-Conductor Cables
89
1
4-Conductor Cables
90
2
Device Bay
92
3
Chapter 6: The Electrical Interface
95
46
Overview
95
2
Common Mode Signaling
96
1
Differential Signaling
96
1
Recognition of Device Attachment and Detachment
97
4
IEEE 1394-1995 Device Attachment/Detachment
97
2
IEEE 1394a Device Attachment/Detachment
99
1
Bus Idle State
100
1
The Port Interface
101
3
Differential Signal Specifications
104
1
Arbitration Signaling
105
5
Line State Signaling (1, 0, and Z)
105
2
Line State Detection
107
3
Reset Signaling
110
1
Line States During Configuration
110
2
Line States During Normal Arbitration
112
2
Starting and Ending Packet Transmission
114
2
Dribble Bits
116
1
Port State Control
116
1
Speed Signaling
117
5
High Speed Devices Slowed Due to Topology
118
1
Devices of Like Speed Directly Connected
118
1
Speed Signaling Circuitry
119
3
Data/Strobe Signaling
122
3
NRZ Encoding
123
1
Data-Strobe Encoding
124
1
Gap Timing
125
3
Cable Interface Timing Constants
128
5
Suspend/Resume
133
1
Cable Power
133
8
Cable Power Requirements
134
1
Power Class
135
2
Power Distribution
137
1
Bus Powered Nodes
138
3
Chapter 7: Arbitration
141
24
Overview
141
1
Arbitration Signaling
142
3
Arbitration Services
145
2
Asynchronous Arbitration
147
3
Fairness Interval
147
1
Arbitration Enable Bit
147
1
Fair Arbitration Service
148
1
Arbitration Reset Gap
148
2
The Acknowledge Packet and Immediate Arbitration Service
150
1
Isochronous Arbitration
150
2
Cycle Start and Priority Arbitration
152
1
Combined Isochronous and Asynchronous Arbitration
152
5
Cycle Start Skew
152
5
1394a Arbitration Enhancements
157
6
Acknowledge Accelerated Arbitration
157
1
Fly-by Arbitration
158
1
Acceleration Control
159
2
Priority Arbitration Service
161
2
Summary of Arbitration Types
163
2
Chapter 8: Asynchronous Packets
165
34
Asynchronous Packets
165
9
Data Size
167
1
Write Packets
168
6
Asynchronous Stream Packet
174
1
Read Packets
175
8
Lock Operations
183
7
Lock Request Packet
183
3
Lock Transaction Types (Extended t_code Field)
186
1
Data Block Length During Lock Request
187
1
Lock Response Packet
188
2
Response Codes
190
1
Acknowledge Packet
191
2
Asynchronous Transaction Summary
193
2
Write Transactions
193
1
Summary of Read and Lock Transactions
194
1
Cycle Start Packet
195
4
Chapter 9: Isochronous Packet
199
6
Stream Data Packet
199
2
Isochronous Data Packet Size
201
1
Isochronous Transaction Summary
202
3
Chapter 10: PHY Packet Format
205
16
Overview
205
1
PHY Packet Format
206
1
Self-ID Packets
207
5
Self-ID Packet Zero
207
3
Self-ID Packets One, Two, and Three (1394-1995)
210
1
Self-ID Packets One and Two (1394a)
211
1
Link-on Packet
212
1
PHY Configuration Packet
213
1
Force Root Node
213
1
Gap Count Optimization
214
1
Extended PHY Packets
214
7
Ping Packet
214
1
Remote Access Packet
215
1
Remote Reply Packet
216
1
Remote Command Packet
217
1
Remote Confirmation Packet
218
1
Resume Packet
219
2
Chapter 11: Link to PHY Interface
221
26
Overview
221
1
The Interface Signals
222
2
Sharing the Interface
224
3
PHY Initiated Transfers
224
1
Idle State
225
1
Status State
225
1
Receive State
225
1
Grant State
225
1
Link Initiated Transfers
226
1
Determining Transfer Rate Between Link and PHY
227
1
Powering the Link
228
1
Packet Transmission
228
8
Link Issues Request
228
3
Request Types
231
1
Speed of Link to PHY Data Transmission
231
1
When Can the Link Issue a Request?
232
2
PHY Behavior When a Packet Request is Received
234
2
Receiving Packets
236
2
Speed of PHY to Link Data Transmission
237
1
PHY Reports Status
238
2
ARB_RESET_GAP
239
1
SUBACTION_GAP
239
1
BUS_RESET_START
239
1
PHY_INTERRUPT
240
1
Accelerated Arbitration Control
240
1
Accessing the PHY Registers
241
4
PHY Register Reads
242
1
When Can a Register Read Request Be Issued?
243
1
PHY Behavior When a Register Read Request is Received
243
1
Register Contents Returned by PHY
243
1
PHY Register Writes
244
1
When Can a PHY Register Write Request Be Issued?
244
1
PHY Behavior When a Register Write Request is Received
245
1
Electrical Isolation Between PHY and Link
245
2
Chapter 12: Transaction Retry
247
18
Overview
247
1
Busy Retry
248
11
The First Packet Transmission Attempt
248
1
Single Phase Retry
249
1
Sending-Node Retry Behavior (Outbound Retry)
249
1
Receiving-Node Retry Behavior (Inbound Retry)
250
1
Dual Phase Retry
251
1
Sending-Node Retry Behavior (Outbound Retry)
252
3
Receiving-Node Retry Behavior (Inbound Retry)
255
4
Transactions Errors
259
6
Packet Transmission Errors
259
3
Packet Error Handling Summary
262
3
Part Three Serial Bus Configuration
265
64
Chapter 13: Configuration Process
265
8
Overview
265
2
Bus Initialization (Bus Reset)
267
1
Tree Identification (The Family Tree)
268
2
Self Identification
270
2
Bus Management
272
1
Chapter 14: Bus Reset (Initialization)
273
12
Overview
273
1
Sources of Bus Reset
274
1
Power Status Change
274
1
Bus Reset Signaled by Attached Node
274
1
Node Attachment or Removal
275
1
MAX_ARB_STATE_TIME Expires
275
1
Software Initiated Bus Reset
275
1
Bus Reset Signaling
275
2
Effects of Bus Reset
277
2
Topology Information Cleared
277
1
PHY Register Changes
277
1
Port Bias and Connected Bits
278
1
Port_Event Bit
278
1
Initiate Bus Reset (IBR) and Initiate Short Bus Reset (ISBR)
278
1
Physical_ID Field
278
1
Gap_Count
278
1
CSR Register Changes
279
1
1394-1995 and Reset Runaway
279
6
Problem One: The Reset Storm
279
1
The 1394a Solution: Debounce Port Status Signal
280
2
Problem Two: Recognition of Connection Change Not Symmetric
282
1
The Solution: Slow Node Accepts Fast Node's Reset Signaling
282
1
Problem Three: Reset Signaled During Packet Transmission
282
1
1394a Solution: Arbitrated Bus Reset
283
2
Chapter 15: Tree Identification
285
20
Overview
285
1
Tree ID Signaling
286
1
The Tree ID Process
286
4
Leaf Nodes Try to Find Their Parents
287
1
Parents Identify Their Children
288
2
Three Example Scenarios
290
1
Scenario One
290
3
Leaf Nodes Signal Parent_Notify
290
2
Branch Nodes Locate Their Parents
292
1
Scenario Two
293
5
Leaf Nodes Locate Their Parents
294
1
Root Contention
295
3
Scenario Three
298
6
Force Root Delay
299
1
Leaf Nodes Attempt to Locate Their Parents
300
1
Branch Nodes Attempt to Locate Their Parents
300
4
Looped Topology Detection
304
1
Chapter 16: Self Identification
305
24
Overview
305
1
Self-Identification Signaling
306
1
Physical ID Selection
306
17
First Physical ID is Assigned
306
1
Self-ID Count
307
1
Branch Nodes Signal Arbitration Grant & Data Prefix
308
2
Node A Broadcasts Its Self-ID Packet
310
1
Node A Signals Self-Identification Done
311
1
Nodes Exchange Speed Information
312
1
Second and Subsequent Physical ID Assignment
313
1
Second Self-ID Assignment
314
2
Third Physical ID Assignment
316
2
Fourth Physical ID Assignment
318
2
Fifth Physical ID Assignment
320
2
Final Physical ID Always Belongs to Root Node
322
1
Self-ID Packets
323
6
Self-ID Packet Zero
323
2
Self-ID Packets One and Two (1394a)
325
1
Who Uses the Self-ID Packet Information
326
3
Part Four Serial Bus Management
329
32
Chapter 17: Cycle Master
329
4
Overview
329
1
Determining and Enabling the Cycle Master
329
1
Cycle Start Packet
330
3
Chapter 18: Isochronous Resource Manager
333
10
Overview
333
1
Determining the Isochronous Resource Manager
334
1
Minimum Requirements of Isochronous Resource Managers
335
1
Enabling the Cycle Master
335
1
Resource Allocation Registers
336
6
Channel Allocation
337
1
Channels Available Register Format
337
1
Accessing the Channels Available Register
337
2
Bus Bandwidth Allocation
339
1
Bandwidth Available Register Format
340
1
Accessing the Bandwidth Available Register
340
1
Bus Bandwidth Set-Aside for Asynchronous Transactions
341
1
Reallocation of Isochronous Resources
342
1
Power Management
342
1
Chapter 19: Bus Manager
343
8
Overview
343
1
Determining the Bus Manager
344
1
Power Management
345
1
Power Management by Bus Manager Node
345
1
Power Management by IRM Node
346
1
The Topology Map
346
3
Accessing the Topology Map
347
1
Gap Count Optimization
348
1
The Speed Map
349
1
Accessing the Speed Map
349
1
Bus Bandwidth Set-Aside
350
1
Chapter 20: Bus Management Services
351
10
Overview
351
2
Serial Bus Control Requests
353
3
Bus Reset Control Request
353
1
Initialize Control Request
354
1
Link-On Control Request
354
1
Present Status
354
1
PHY Configuration Request
354
1
Set Force Root and Set Gap Count
355
1
Extended PHY Packets
355
1
Serial Bus Control Confirmations
356
1
Serial Bus Event Indication
357
4
Part Five Registers & ROM
361
66
Chapter 21: CSR Architecture
361
32
Overview
361
1
Core Registers
362
14
Effect of Reset on the CSRs
364
1
State Register (State_Clear & State_Set)
364
1
State_Clear Register
365
1
State_Set Register
366
1
Bus Depend Field
366
1
Cycle Master Enable
367
2
Abdicate
369
1
Node_IDS Register
369
4
Reset_Start Register
373
1
Indirect_Address and Indirect_Data Registers
373
1
Split_Timeout Register
373
2
Argument, Test_Start, and Test_Status Registers
375
1
Units_Base, Units_Bound, Memory_Base, and Memory_Bound Registers
375
1
Interrupt_Target and Interrupt_Mask Registers
375
1
Clock_Value, Clock_Tick_Period, Clock_Strobe_Arrived, and Clock_Info Registers
376
1
Message_Request & Message_Response Registers
376
1
Serial Bus Dependent Registers
376
12
Cycle_Time & Bus_Time Registers
377
3
Power_Fail_Imminent & Power_Source Registers
380
2
Busy_Timeout Register
382
1
Bus_Manager_ID Register
383
1
Bandwidth_Available Register
384
1
Channels_Available Register
384
2
Maint_Control Register
386
1
Maint_Utility Register
386
2
Unit Registers
388
5
Topology Map
389
1
Speed Map
390
3
Chapter 22: PHY Registers
393
16
Overview
393
1
1394-1995 PHY Register Map
394
4
Port Status Registers
397
1
PHY Configuration Packet
397
1
Root Hold Off
397
1
Gap Count Optimization
397
1
1394a PHY Register Map
398
11
Page Select
402
1
Port Status Register Page
403
4
Vendor Identification Register Page
407
1
Vendor-dependent Page
408
1
Chapter 23: Configuration ROM
409
18
Overview
409
1
Minimal ROM Format
410
1
General ROM Format
410
13
Header Information
411
1
Info_Length
411
1
CRC_Length
412
1
CRC_Value
412
1
Bus_Info_Block (1394-1995)
412
1
Bus_Name Field
413
1
Bus Characteristics Fields
413
1
Node_Vendor_ID Field
414
1
Chip_ID Fields
415
1
Bus Info Block (1394a)
415
1
Power Management Capable
415
1
Generation Field
416
1
Link Speed
416
1
Root_Directory
416
3
Required Root Directory Entries
419
1
Module_Vendor_Id
419
1
Node_Capabilities
419
1
Node_Unique_Id
420
2
Unit_Directory & Unit_Power_Requirements
422
1
Optional Root Directory Entries
422
1
Bus_Dependent_Info
422
1
Module_Hw_Version
422
1
Module_Spec_Id
422
1
Module_Sw_Version
422
1
Company ID Value Administration
423
4
Part Six Power Management
427
68
Chapter 24: Introduction to Power Management
427
4
Overview
427
1
Review of 1394-1995 Power-Related Issues
428
1
Goals of the 1394a Power Extensions
429
2
Chapter 25: Cable Power Distribution
431
14
Power Distribution
431
14
Power Class Codes
432
1
Power Providers
433
1
Power Provider Classes
434
2
Alternate Power Providers
436
1
Maximum Voltage is less than 20vdc
436
1
Maximum Voltage is Greater than 20vdc
436
1
Power Consumer
437
1
Self-Powered Nodes (Non Power Providers)
438
1
Self-Powered Class Zero Nodes
439
1
Self-Powered Class Four Nodes
440
1
Two port node -- no cable power used
440
1
Three ports or more -- no cable power used
441
1
Two ports or more -- cable power used when power is lost
441
1
Two ports or more -- cable-powered PHY
442
1
Local Power Down Summary
443
2
Chapter 26: Suspend & Resume
445
14
Overview
445
3
Suspending a Port
448
6
Suspending Via the Suspend Command Packet
449
2
Suspending Via RX_SUSPEND
451
1
The BIAS Handshake
451
1
Suspending Via Port Disable
451
1
Disable Via Disable Port Command Packet (local or remote)
452
1
Port Suspend Via Unexpected Loss of Bias
453
1
Resuming Full Operation
454
5
Resuming Via Resume Packet
454
1
Resuming Via Resume Port Command Packet
454
1
Resuming Via Port Events
455
4
Chapter 27: Power State Management
459
20
Power Management
459
20
Power States
460
1
Node Power States
460
1
Node Power State Zero (N0)
461
1
Node Power State One (N1)
461
1
Node Power State Two (N2)
461
1
Node Power State Three (N3)
461
1
Unit Power States
461
2
New CSRs
463
1
Node Power Control Register
464
2
Notification Address Register
466
1
Cable Power Source State Register
466
1
Cable Power Source Control Register
467
1
Power Change Register
468
1
Unit Power State Register
469
1
Unit Power Control Register
470
1
Battery State Register
471
1
New ROM Entries
472
1
Node Power Directory Entry
473
1
Node Power Level Entry
474
1
Cable Power Source Level Entry
475
1
Node Power Management Entry
475
1
Battery Group Entry (Node)
476
1
Battery State Entry
476
1
Unit Power Directory Entry
477
1
Unit Power Level Entry
477
1
Unit Power Management Entry
477
1
Battery Group Entry (Unit)
478
1
Appendix: Example 1394 Chip Solutions
479
16
Overview
479
1
1394 in the PC
479
10
TSB12LV22 / OHCI-Lynx
480
1
Features
480
1
Overview
481
1
Block Diagram
482
1
TSB41LV03
482
1
Features
483
1
TSB41LV03 Overview
483
4
Block Diagram
487
1
Putting it all Together
488
1
1394 in the Digital Camera
489
5
TSB12LV31 -- GPLynx
489
1
Features
489
1
Overview
490
1
Block Diagram
491
1
TSB21LV03A
492
1
Features
492
1
Block Diagram
493
1
Putting it all Together
494
1
For More Information
494
1
Appendix: Glossary
495
8
Index
503