Copyright ©1998-2010 Glenn Fleishman. Send in your comments. Bibliographic information on isbn.nu licensed from Baker & Taylor. Contact them for corrections and licensing, or read more about our data.
Tables of Contents for Firewire System Architecture
Chapter/Section Title
Page #
Page Count
The MindShare Architecture Series
1
1
Cautionary Note
2
1
Organization of This Book
2
3
Part One: Introduction to FireWire (IEEE 1394)
2
1
Chapter 1: Why FireWire?
2
1
Chapter 2: Overview of the FireWire Architecture
2
1
Part Two: Serial Bus Communications
3
1
Chapter 3: Communication Model
3
1
Chapter 4: Cables & Connectors
3
1
Chapter 5: The Electrical Interface
3
1
Chapter 6: Arbitration
3
1
Chapter 7: Asynchronous Transactions
3
1
Chapter 8: Isochronous Transactions
3
1
Chapter 9: Transaction Retry
3
1
Part Three: Registers and Configuration ROM
4
1
Chapter 10: CSR Architecture
4
1
Chapter 11: Configuration ROM
4
1
Chapter 12: PHY Registers
4
1
Part Four: Serial Bus Configuration
4
1
Chapter 13: Configuration Process
4
1
Chapter 14: Bus Initialization
4
1
Chapter 15: Tree Identification
4
1
Chapter 16: Self Identification
4
1
Chapter 17: Cycle Master
4
1
Chapter 18: Isochronous Resource Manager
5
1
Chapter 19: Bus Management
5
1
Chapter 20: Power Management
5
1
Part Five: Miscellaneous
5
1
Chapter 21: Link to PHY Interface
5
1
Chapter 22: Example 1394 Chip Solutions
5
1
Target Audience
5
1
Prerequisite Knowledge
5
1
Documentation Conventions
6
1
Labels for Multi-byte Blocks
6
1
Hexadecimal Notation
6
1
Binary Notation
6
1
Decimal Notation
7
1
Bit Versus Byte Notation
7
1
Identification of Bit Fields (logical groups of bits or signals)
7
1
Visit Our Web Page
8
1
We Want Your Feedback
8
3
Part One: Introduction to FireWire (IEEE 1394)
11
26
Chapter 1: Why FireWire?
11
6
Overview
11
1
Motivations Behind FireWire Development
11
3
Inexpensive Alternate to Parallel Buses
12
1
Plug and Play Support
12
1
Eliminate Host Processor/Memory Bottleneck
12
1
High Speed Bus with Scalable Performance
13
1
Support for Isochronous Applications
13
1
BackPlane and Cable Environments
13
1
Bus Bridge
13
1
1394 Applications
14
1
IEEE 1394 Refinements
14
1
Primary Features
15
2
Chapter 2: Overview of the FireWire Architecture
17
20
Specifications & Related Documents
17
2
IEEE 1394-1995 and the IEEE 1394a Supplement
18
1
IEEE 1394.B
18
1
IEEE 1394 Overview
19
1
Topology
19
3
Multiport Nodes and Repeaters
21
1
Configuration
21
1
Peer-To-Peer Transfers
21
1
Device Bay
22
1
The ISO/IEC 13213 Specification
22
11
Node Architecture
23
1
Address Space
24
4
Transfers and Transactions
28
3
Isochronous Transfers
28
1
Asynchronous Transfers
29
2
Control and Status Registers (CSRs)
31
1
Configuration ROM
32
1
Message Broadcast
32
1
Interrupt Broadcast
32
1
Automatic Configuration
33
4
Part Two: Serial Bus Communications
37
154
Chapter 3: Communications Model
37
26
Overview
37
3
Transfer Types
40
2
Isochronous
40
1
Asynchronous
41
1
The Protocol Layers
42
16
Bus Management Layer
43
1
Transaction Layer
44
3
Transaction Layer Services
45
2
Link Layer
47
5
Split Transactions
48
2
Concatenated Transactions
50
1
Unified Transactions
51
1
Physical Layer
52
6
Twisted Pair Signaling
53
1
Bus Configuration
54
1
Arbitration
54
1
Data Transmission
54
1
Power Pair
54
1
Packet-Based Transactions
55
2
Isochronous Packet
56
1
Port Repeater
57
1
A Sample Asynchronous Transaction
58
3
The Request
59
1
The Response
59
2
An Example Isochronous Transaction
61
2
Chapter 4: Cables & Connectors
63
10
Cable and Connector Types
63
4
6-pin Connector (1394-1995)
64
1
Make First/Break Last Power Pins
65
1
Optional 4-pin Connector (1394a supplement)
65
1
Positive Retention
66
1
Cable Characteristics
67
3
6-Conductor Cables
67
1
4-Conductor Cables
68
2
Device Bay
70
3
Chapter 5: The Electrical Interface
73
30
Overview
73
4
Common Mode Signaling
74
1
Differential Signaling
74
3
Recognition of Device Attachment and Detachment
77
1
Bus Idle State
78
1
Arbitration Signaling
78
8
Line State Signaling (1, 0, and Z)
79
1
Line State Detection
80
3
Signaling During Normal Arbitration
83
2
Signaling States During Configuration
85
1
Reset Signaling
86
1
Starting and Ending Packet Transmission
87
1
Data/Strobe Signaling
88
9
Speed Signaling
88
5
High Speed Devices Slowed Due to Topology
89
1
Devices of Like Speed Directly Connected
90
1
Speed Signaling Circuitry
91
2
NRZ Encoding
93
1
Data-Strobe Encoding
94
1
Gap Timing
95
2
Cable Power
97
6
Cable Power Requirements
98
1
Power Class
98
1
Power Distribution
99
1
Bus Powered Nodes
100
3
Functional Units That Consume Additional Bus Power
101
2
Chapter 6: Arbitration
103
20
Overview
103
1
Arbitration Signaling
104
2
Asynchronous Arbitration
106
3
Fairness Interval
107
1
Arbitration Reset Gap
107
1
Immediate Arbitration
107
2
Isochronous Arbitration
109
1
Cycle Start and Priority Arbitration
109
1
Combined Isochronous and Asynchronous Arbitration
109
5
Cycle Start Skew
112
2
1394a Arbitration Enhancements
114
9
Acknowledge Accelerated Arbitration
116
1
Fly-by Arbitration
117
1
Token-style Arbitration
118
1
Acceleration Control
118
2
Priority Arbitration
120
3
Chapter 7: Asynchronous Transactions
123
42
Overview
123
1
Anatomy of Asynchronous Transactions
124
12
The Request Subaction
124
7
Initiating the Transaction (The Request)
127
2
Transaction Layer
127
1
The Link Layer
127
1
The PHY Layer
128
1
Receiving the Request (The Indication)
129
2
Physical Layer
129
1
Link Layer
129
1
Transaction Layer
130
1
The Acknowledgment
130
1
Response Subaction
131
5
Reporting the Results (The Response)
132
2
Transaction Layer Response
132
1
Link Layer Response
133
1
PHY Layer Response
133
1
Response Reception
134
2
Physical Layer
134
1
Link Layer
134
1
Transaction Layer
135
1
The Acknowledgment
135
1
Transaction Label
136
1
Asynchronous Packets
136
8
Write Packets
138
6
Asynchronous Stream Packet
144
1
Read Packets
145
8
Lock Operations
153
6
Lock Request Packet
153
6
Response Codes
159
1
Acknowledge Packet
159
2
Asynchronous Transaction Summary
161
2
Write Transactions
161
1
Summary of Read and Lock Transactions
162
1
Cycle Start Packet
163
2
Chapter 8: Isochronous Transactions
165
8
Overview
165
1
Setting Up Isochronous Transactions
166
1
Maintaining Synchronization
166
1
Anatomy of Isochronous Transactions
167
3
Isochronous Transaction Initiation & Reception
167
3
Initiating the Transaction
168
1
Link Layer
168
1
The PHY Layer
168
1
Transaction Reception
169
1
Physical Layer
169
1
Link Layer
170
1
Isochronous Data Block Packet
170
2
Isochronous Transaction Summary
172
1
Chapter 9: Transaction Retry
173
18
Overview
173
1
Busy Retry
174
11
The First Packet Transmission Attempt
174
1
Single Phase Retry
175
2
Sending-Node Retry Behavior (Outbound Retry)
175
1
Receiving-Node Retry Behavior (Inbound Retry)
176
1
Dual Phase Retry
177
8
Sending-Node Retry Behavior (Outbound Retry)
178
3
Receiving Node Retry Behavior (Inbound Retry)
181
4
Transactions Errors
185
6
Packet Transmission Errors
185
3
Packet Error Handling Summary
188
3
Part Three: Registers and Configuration ROM
191
62
Chapter 10: CSR Architecture
191
30
Overview
191
1
Core Registers
192
13
Effect of Reset on the CSRs
194
1
State Register (State_Clear & State_Set)
194
3
State_Clear Register
195
2
State_Set Register
197
2
Node_IDS Register
199
3
Reset_Start Register
202
1
Indirect_Address and Indirect_Data Registers
202
1
Split_Timeout Register
202
2
Argument, Test_Start, and Test_Status Registers
204
1
Units_Base, Units_Bound, Memory_Base, and Memory_Bound Registers
204
1
Interrupt_Target and Interrupt_Mask Registers
204
1
Clock_Value, Clock_Tick_Period, Clock_Strobe_Arrived, and Clock_Info Registers
205
1
Message_Request & Message_Response Registers
205
1
Serial Bus Dependent Registers
205
12
Cycle_Time & Bus_Time Registers
206
3
Power_Fail_Imminent & Power_Source Registers
209
2
Busy_Timeout Register
211
1
Bus_Manager_ID Register
212
1
Bandwidth_Available Register
213
1
Channels_Available Register
213
2
Maint_Control Register
215
1
Maint_Utility Register
215
2
Unit Registers
217
3
Topology Map
217
2
Speed Map
219
1
New 1394a Defined Registers
220
1
Chapter 11: Configuration ROM
221
14
Overview
221
1
Minimal ROM Format
222
1
General ROM Format
222
12
Header Information
223
1
Info_Length
223
1
CRC_Length
224
1
CRC_Value
224
1
Bus_Info_Block
224
3
Bus_Name Field
225
1
Bus Characteristics Fields
225
1
Node_Vendor_ID Field
226
1
Chip_ID Fields
227
1
Root_Directory
227
6
Required Root Directory Entries
230
3
Module_Vendor_Id
230
1
Node_Capabilities
230
1
Node_Unique_Id
231
2
Unit_Directory & Unit_Power_Requirements
233
1
Optional Root Directory Entries
233
1
Bus_Dependent_Info
233
1
Module_Hw_Version
233
1
Module_Spec_Id
233
1
Module_Sw_Version
233
1
Company ID Value Administration
234
1
Chapter 12: PHY Registers
235
18
Overview
235
1
1394-1995 PHY Register Map
236
4
Port Status Registers
238
1
PHY Configuration Packet
239
1
Root Hold Off
239
1
Gap Count Optimization
239
1
1394a PHY Register Map
240
13
Page Select
243
10
Port Status Register Page
244
4
Vendor Identification Register Page
248
5
Part Four: Serial Bus Configuration
253
110
Chapter 13: Configuration Process
253
8
Overview
253
1
Bus Initialization (Bus Reset)
254
1
Tree Identification (The Family Tree)
255
2
Self Identification
257
2
Bus Management
259
2
Chapter 14: Bus Initialization
261
4
Bus Reset
261
3
Sources of Bus Reset
262
1
Power Status Change
262
1
Node Attachment or Removal
262
1
Software Initiated Reset
262
1
Bus Reset Signaling
262
1
Effects of Bus Reset
263
1
Reset Storm
264
1
Chapter 15: Tree Identification
265
20
Overview
265
1
Scenario One
266
7
Tree ID Signaling
266
2
The Tree ID Process
268
1
Leaf Nodes Locate Their Parents
268
3
Branch Nodes Locate Their Parents
271
2
Scenario Two
273
5
Leaf Nodes Locate Their Parents
274
1
Root Contention
275
3
Scenario Three
278
6
Force Root Delay
279
1
Leaf Nodes Attempt to Locate Their Parents
280
1
Branch Nodes Attempt to Locate Their Parents
280
4
Looped Topology Detection
284
1
Chapter 16: Self Identification
285
24
Overview
285
1
Self-Identification Signaling
286
1
Physical ID Selection
286
17
First Physical ID is Assigned
286
1
Self-ID Count
287
1
Branch Nodes Signal Arbitration Grant & Data Prefix
288
3
Node A Signals Self-Identification Done
291
1
Nodes Exchange Speed Information
292
1
Second and Subsequent Physical ID Assignment
293
10
Second Self-ID Assignment
294
2
Third Physical ID Assignment
296
2
Fourth Physical ID Assignment
298
2
Fifth Physical ID Assignment
300
2
Final Physical ID Always Belongs to Root Node
302
1
Self-ID Packets
303
6
Self-ID Packet Zero
303
2
Self-ID Packets One, Two & Three
305
3
Self-ID Packet Eight
306
2
Who Uses the Self-ID Packet Information
308
1
Chapter 17: Cycle Master
309
4
Overview
309
1
Determining and Enabling the Cycle Master
309
1
Cycle Start Packet
310
3
Chapter 18: Isochronous Resource Management
313
10
Overview
313
1
Determining the Isochronous Resource Manager
314
1
Minimum Requirements of Isochronous Resource Managers
315
1
Enabling the Cycle Master
315
1
Resource Allocation Registers
316
6
Channel Allocation
317
3
Channels Available Register Format
317
1
Accessing the Channels Available Register
317
3
Bus Bandwidth Allocation
320
2
Bandwidth Available Register Format
320
1
Accessing the Bandwidth Available Register
320
2
Bus Bandwidth Set-Aside for Asynchronous Transactions
322
1
Reallocation of Isochronous Resources
322
1
Power Management
322
1
Chapter 19: Bus Management
323
8
Overview
323
1
Determining the Bus Manager
324
1
Power Management
325
1
Power Management by Bus Manager Node
325
1
Power Management by IRM Node
326
1
The Topology Map
326
3
Accessing the Topology Map
327
1
Gap Count Optimization
328
1
The Speed Map
329
1
Accessing the Speed Map
329
1
Bus Bandwidth Set-Aside
330
1
Chapter 20: Power Management
331
32
Overview
331
1
Review of 1394-1995 Power-Related Issues
332
1
Goals of the 1394a Power Extensions
333
1
Power Distribution
333
8
Power Class Codes
334
1
Power Providers
335
4
Primary Power Providers
337
1
Secondary Power Providers
338
1
Power Consumers
339
2
Self-Powered Nodes (Non Power Providers)
339
2
Local Power Down Summary
341
1
Power Management
341
19
Power States
342
3
Node Power States
342
2
Node Power State Zero (NO)
343
1
Node Power State One (N1)
343
1
Node Power State Two (N2)
343
1
Node Power State Three (N3)
343
1
Unit Power States
344
1
New CSRs
345
9
Node Power Control Register
346
2
Notification Address Register
348
1
Cable Power Source State Register
348
1
Cable Power Source Control Register
349
1
Power Change Register
350
2
Unit Power State Register
352
1
Unit Power State Control Register
352
2
Battery State Register
354
1
New ROM Entries
354
6
Node Power Directory Entry
355
1
Node Power Level Entry
356
1
Cable Power Source Level Entry
357
1
Node Power Management Entry
357
1
Battery Group Entry (Node)
358
1
Battery State Entry
358
1
Unit Power Directory Entry
359
1
Unit Power Level Entry
359
1
Unit Power Management Entry
359
1
Battery Group Entry (Unit)
360
1
Suspend and Resume
360
3
Part Five: Miscellaneous
363
40
Chapter 21: Link to PHY Interface
363
24
Overview
363
1
The Interface Signals
364
2
Sharing the Interface
366
3
Link Initiated Transfers
366
1
PHY Initiated Transfers
367
2
Idle State
368
1
Status State
368
1
Receive State
368
1
Grant State
369
1
Determining Transfer Rate Between Link and PHY
369
1
Powering the Link
369
1
Packet Transmission
370
7
Link Issues Request
370
7
Request Types
372
1
Speed of Link to PHY Data Transmission
372
1
When Can the Link Issue a Request?
373
3
PHY Behavior When a Packet Request is Received
376
1
Receiving Packets
377
2
Speed of PHY to Link Data Transmission
378
1
Accessing the PHY Registers
379
3
PHY Register Reads
380
1
When Can a Register Read Request Be Issued?
380
1
PHY Behavior When a Register Read Request is Received
380
1
Register Contents Returned by PHY
380
1
PHY Register Writes
381
1
When Can a PHY Register Write Request Be Issued?
382
1
PHY Behavior When a Register Write Request is Received
382
1
PHY Reports Status
382
2
ARB_RESET_GAP
383
1
SUBACTION_GAP
383
1
BUS_RESET_START
384
1
PHY_INTERRUPT
384
1
Fly-By Arbitration Control
384
1
Electrical Isolation Between PHY and Link
385
2
Chapter 22: Example 1394 Chip Solutions
387
16
Overview
387
1
1394 in the PC
387
10
TSB12LV22 / OHCI-Lynx
388
1
FEATURES
388
1
OVERVIEW
389
1
BLOCK DIAGRAM
390
1
TSB41LV03
390
6
FEATURES
391
1
TSB41LV03 OVERVIEW
391
4
Block Diagram
395
1
Putting it all Together
396
1
1394 in the Digital Camera
397
5
TSB12LV31 -- GPLynx
397
3
Features
397
1
Overview
398
1
Block Diagram
399
1
TSB21LV03A
400
2
FEATURES
400
1
BLOCK DIAGRAM
401
1
Putting it all Together
402
1
For More Information
402
1
Appendix: Glossary
403
8
Index
411