Copyright ©1998-2010 Glenn Fleishman. Send in your comments. Bibliographic information on isbn.nu licensed from Baker & Taylor. Contact them for corrections and licensing, or read more about our data.
Tables of Contents for Specc
Chapter/Section Title
Page #
Page Count
List of Figures
ix
List of Tables
xiii
Preface
xv
Acknowledgments
xvii
Introduction
1
12
System Level Design Challenge
1
5
Platform Approach
2
1
IP Assembly
3
1
Synthesis from Specifications
4
1
System Level Design Language
5
1
Related Work
6
5
University projects
6
2
Commercial systems
8
1
Open Consortia
9
2
SpecC Goals
11
1
Summary
11
2
Essential Issues in System Level Design
13
42
Models
14
10
Finite-state machines
14
2
Dataflow graph
16
1
Finite-state machine with datapath
17
2
Programming languages
19
1
Superstate FSMD
20
1
Hierarchical concurrent finite-state machines
20
2
Program-state machines
22
2
Architectures
24
10
Controller architecture
24
1
Datapath architecture
25
3
Processor architecture
28
1
CISC architecture
29
2
RISC architecture
31
1
VLIW architecture
32
1
SOC architecture
33
1
Languages
34
13
Concurrency
35
2
State transitions
37
1
Hierarchy
38
2
Programming constructs
40
1
Behavioral completion
41
1
Exception handling
41
1
Timing
42
1
Communication
42
3
Process synchronization
45
2
Methodology
47
6
IP Requirements
48
3
Synthesis Flow
51
1
Analysis and Validation Flow
51
1
Backend
52
1
Summary
53
2
The Specc Language
55
14
Design Considerations for System Level Design Language
55
1
Traditional Languages
56
1
The SpecC language
57
8
Structural Hierarchy
57
1
Behavioral Hierarchy
58
3
Synchronization
61
1
Exception Handling
61
2
Timing
63
2
Additional features
65
1
Reuse and IP
65
2
Reference Implementation
67
1
Summary
68
1
The Specc Methodology
69
36
Overview
69
3
Specification
72
31
Specification Model
73
3
Architecture exploration
76
16
Communication Synthesis
92
9
Backend
101
2
Summary
103
2
System Level Design With Specc
105
70
GSM Enhanced Full Rate Vocoder
105
3
Human Vocal Tract
106
1
Speech Synthesis Model
106
1
Speech Encoding and Decoding
107
1
Specification
108
7
General
108
1
Vocoder Specification
108
7
Architecture Exploration
115
25
Exploration Flow
117
1
Analysis and Estimation
118
7
Architecture Allocation
125
5
Partitioning
130
5
Scheduling
135
3
Results
138
2
Communication Synthesis
140
12
Protocol Insertion
141
1
Transducer Synthesis
141
1
Protocol Inlining
142
1
Vocoder Communication Synthesis
143
9
Results
152
1
Backend
152
18
Software Synthesis
153
4
Custom Hardware Synthesis
157
13
Summary
170
5
Conclusions
175
2
Appendices
177
134
A-- The SpecC Language Reference Manual
177
24
A.1 Syntax and Semantics
177
1
A.1.1 Boolean Type
177
1
A.1.2 Bitvector Type
178
2
A.1.3 Event Type
180
1
A.1.4 Time Type
180
1
A.1.5 Behavior Class
181
2
A.1.6 Channel Class
183
2
A.1.7 Interface Class
185
1
A.1.8 Ports
186
1
A.1.9 Class Instatiation
187
1
A.1.10 Sequential Execution
188
1
A.1.11 Parallel Execution
189
1
A.1.12 Pipelined Execution
190
2
A.1.13 Finite State Machine Execution
192
1
A.1.14 Exception Handling
193
1
A.1.15 Synchronization
194
2
A.1.16 Timing Specification
196
1
A.1.17 Binary Import
197
1
A.1.18 Persistent Annotation
198
1
A.2 Summary
199
2
B-- Vocoder Description
201
110
B.1 C Reference Implementation Block Diagrams
201
1
B.1.1 Coder
202
6
B.1.2 Decoder
208
3
B.2 Vocoder Specification
211
1
B.2.1 General (shared) behaviors
211
1
B.2.2 Coder
211
13
B.2.3 Decoder
224
7
B.3 Specification Model
231
1
B.3.1 Testbench
231
1
B.3.2 Coder
232
7
B.3.3 Preprocessing
239
1
B.3.4 Linear Prediction Analysis
240
5
B.3.5 Open-Loop Pitch Analysis
245
3
B.3.6 Closed-Loop Pitch Analysis
248
6
B.3.7 Algebraic (fixed) codebook search
254
5
B.3.8 Filter memory updates
259
2
B.3.9 Postprocessing
261
1
B.4 Architecture Model
262
1
B.4.1 Coder
262
1
B.4.2 Bus
263
3
B.4.3 DSP
266
9
B.4.4 HW
275
1
B.5 Communication Model
276
1
B.5.1 Coder
277
1
B.5.2 Bus
277
2
B.5.3 DSP
279
3
B.5.4 HW
282
3
B.6 Implementation Model
285
1
B.6.1 RTL behavioral code
285
2
B.6.2 RTL structural code (control only)
287
24
Index
311